Project Implementation

The low-cost flip chip technology and redistribution will be developed at HKUST mostly in the Microelectronic Fabrication Facility (MFF). Dissemination and technology transfer will be on-going as engineers from companies will be invited to work on-site. Flip-chip modules will be designed, fabricated, redistributed, bumped, bonded and tested at the request of companies. Below are the main steps to implement this project.

Design
The project team members will work with local companies to establish test chip design layouts. The designs will be drawn using the Cadence chip design program.

For companies with wafers from their customers, redistribution is necessary but not a requirement depending on the bond pad pitch. We will design the redistribution routing for the bump pads. Currently, almost 100% of wafers produced in the world are intented for wirebonding. The pads are usually placed in close proximity around the periphery of the die. Redistribution will allow bumps to be arranged uniformly in a grid array or peripherally. The end result is wider pitches reducing the potential of bump-to-bump bridging later on during solder reflow. Several metal and photoresist masks must be designed for this process. Therefore, redistribution to "fan-in" the pads such as shown in the following schematic is needed for bump deposition on most wafers. It should be noted that not all wafers need to be (or can be) redistributed.

	Bond Pads		Bump Pads
Redistribution for wafer level packaging

Fabrication
Companies can select and approve their designs for us to build the test chips in the Microelectronics Fabrication Facility (MFF). The fabrication of test chips involves semiconductor fabrication steps to deposit and make patterns of very small feature sizes on the wafer. Engineering resources will be focused here so that wafer yields are high.

Custom-designed masks can be directly fabricated from the Cadence Design files. These masks will be used to transfer patterns to the insulator or the conductor thin films on the wafer. Patterning of insulator or conductor films on wafers uses photolithography technology. Basically, a photosensitive film (photoresist) is spun on the wafer to a very uniform thin layer prior to soft bake. A mask is aligned over this wafer which is then exposed to light which develops the exposed area on the wafer. Areas covered by the opaque portion of the mask are not developed and can then be removed by a solvent. The exposed underlying insulator or conductor can be etched either by wet acid etch or dry etch revealing the desired pattern. The remaining photoresist is removed and this process is repeated for each layer of the wafer. For wafer redistribution, the photosensitive material will be left on the wafer as part of the building block. Such materials and their processes will be developed and optimised by the group as part of this project.

Under Bump Metallisation
The aluminum pads for the bumps must be pretreated with underbump metal (UBM). HKUST has been using a metal sputtering process, which is not low cost, due it is low throughput and high machine cost. A non-sputter process that will be developed as part of this project will use electroless plating solution supplied by one of our sponsors. The electroless chemical baths must be well understood and controlled to avoid uneven or non plating.

Bumping
Stenciling solder for fine pitch or high density interconnect on wafers is a challenging new technology that will be developed as part of this project. Feature sizes of 0.10 mm have to be stenciled on, requiring extremely thin specially made stencils with 0.08mm thickness. The stencil printing technique allows flexibility in changing from lead solder to lead-free solder by a change in solder paste material. For each type of solder paste, the process will be optimized to obtain uniform bump size with high strength. The potential solders to be evaluated are:

Standard solder:	Sn/Pb-63%/37% (183 oC melting point)
Lead-free solder:	Sn/Bi/Cu - 90.5/8.5/0.5 (198 oC) Sn/Ag - 96.5/3.5 (221oC) Sn/Cu -99/1 (227 oC)

Chip Attach
During this part of the project, companies can have the bumped chip bonded or attached to their product (glass displays, PCB, flex circuits, etc.). Bonding or chip attach is quite critical and the machine doing this requires high placement accuracy. Misalignment and cold solder joints can be observed under the X-ray system. Rework at this point is still possible. After attach, a liquid underfill material will be dispensed into the 0.05mm gap between the chip and the substrate. The underfill material improves the strength of the flip-chip-on-board. However, this process may be the bottleneck in production due to the extended cure times, which limit the throughput. Snap cure underfills and no underfill systems will be evaluated for reliability as part of this project. Optimization of the underfilling process is critical to the reliability of the end-product. Voids, filler settling and delamination can be observed under a scanning acoustic microscope as part of the inspection process. These defects must be minimized for good reliability. Reworkability after underfilling becomes much more complex but is still possible and will be evaluated as part of this study.