Events

 
PhD Thesis Presentation
Design Techniques for Compact and Low-Phase-Noise Frequency Synthesizers

by Zhiqiang HUANG

Date
 :  15 Sep 2017 (Fri)
Time
 :  3pm
Venue  :  Room 4475 (Lifts 25 &26), 4/F Academic Building, HKUST

Examination Committee
Prof Amy Nicole DALTON, MARK/HKUST (Chairperson)
Prof Howard LUONG, ECE/HKUST (Thesis Supervisor)
Prof Jri LEE, Department of Electrical Engineering, National Taiwan University (External Examiner)
Prof Philip MOK, ECE/HKUST
Prof Wing Hung KI, ECE/HKUST
Prof Yi-Kuen LEE, MAE/HKUST
 
Abstract
Motivated by the increasing demand of high-performance communication systems-on-chip, for which frequency synthesizer plays one of the most critical role, this dissertation proposes several design techniques to improve the performance of frequency synthesizers in terms of size, phase noise, frequency, and power. 
 
First, a 2.1-GHz 3rd-order inductor-less frequency synthesizer with compact size is presented. A 3rd-order cascaded phase-locked loop (PLL) architecture is proposed to achieve 40-MHz -3-dB bandwidth to reject oscillator’s phase noise and additional 24-dB rejection for 1-MHz supply-noise. A clock-skew-sampling phase detector is also proposed to achieve high gain and wide detection range and achieve -113dBc/Hz in-band phase noise.
 
Second, an E-band PLL with fully-integrated loop filter is demonstrated. A passive scaling of the loop filter technique is proposed to scale down the capacitor by 100 times and to realize a fully-integrate loop filter with only 0.12 mm2, even with a small loop bandwidth of 50 KHz. The E-band PLL achieves phase noise better than -91.7 dBc/Hz over the 70.5-to-85.5-GHz frequency range.
 
Third, a dithering-less high-resolution 60-GHz DCO is introduced for a low-noise all-digital PLL (ADPLL) with fully integrated loop filter. An exponentially-scaling C-2C switched-capacitor (SC) ladder is proposed for high-frequency resolution. The 60-GHz DCO prototype measures frequency resolution of 4 Hz and operates from 54.79 to 63.16 GHz with phase noise of -90.7~-94.1 dBc/Hz at 1-MHz frequency offset.
 
Finally, a W-band ADPLL with a proposed split transformer as variable inductor for wide tuning range at 100GHz is presented. A dual-path SC ladder is utilized for high frequency resolution and bandwidth variation reduction. A clock-skew-sampling sigma-delta TDC is proposed to achieve an -87-dB/Hz in-band phase noise. With the proposed techniques, the W-band ADPLL measures 10-MHz phase noise from -106 to -110dBc/Hz from 82 to 107.6 GHz. 
 
*** ALL ARE WELCOME !! ***