ECE Seminar
Challenges and Opportunities of Ultimate and Beyond CMOS Devices

Dr. Robert  Chau
Intel Senior Fellow
Director of Transistor Research and Nanotechnology, Intel Corporation

 :  27 Nov 2013 (Wed)
 :  4:30pm - 5:30pm
Venue  :  Classroom 2405 (Lifts 17/18)

For the past forty years relentless focus on Moore’s Law transistor scaling has delivered ever-improving CMOS transistor performance and density. This presentation will discuss architectural and materials options that the research community has been investigating for the ultimate CMOS device [Ref. 1]. In addition, it will review emerging device options beyond the ultimate CMOS device including carbon-based, spin-based, tunnel-based and exciton-based devices that are being researched by universities [Ref. 2]. The challenges and opportunities of ultimate and beyond CMOS devices for future nanoelectronics applications will be discussed. ([Ref. 1]: K. Kuhn, et al., “The Ultimate CMOS Device and Beyond,” IEDM December 2012. [Ref. 2]: K. Bernstein, et al., “Device and Architecture Outlook for Beyond CMOS Switches,” Proceedings of the IEEE, Vol. 98, No. 12, December 2010.)
Robert Chau is an Intel Senior Fellow and Director of Transistor Research and Nanotechnology in the Technology and Manufacturing Group at Intel Corporation. He is responsible for directing research and development in advanced transistors, novel electronic materials, process modules and technologies, and silicon integrated processes for microprocessor and System-on-Chip (SoC) applications. He is also responsible for leading research efforts in emerging nanotechnology for future nanoelectronics applications.
Chau joined Intel in 1989, became an Intel Fellow in 2000 and an Intel Senior Fellow in 2005. During his career at Intel he developed nine generations of Intel gate dielectrics, including the high-k/metal-gate, along with many transistor innovations and process technologies used in various Intel manufacturing processes and microprocessor products. He also introduced many new process modules and device nanotechnologies for Intel's future logic and SoC processes. 
Chau has earned 7 Intel Achievement Awards, including one for the research and development of the Tri-gate transistor technology. He was the co-recipient of the 2008 SEMI Award for North America for the development of Intel's 90nm strained silicon technology, and the 2008 EDN (Electronics Design, Strategy, News) "Innovator of the Year" award for the development of Intel's 45nm high-k metal gate transistor technology. Chau received the 2012 IEEE Jun-ichi Nishizawa Medal for "sustained leadership in developing innovative transistor technologies for advanced logic products." 
Chau received his B.S., M.S. and Ph.D. in electrical engineering from The Ohio State University. He holds more than 270 issued U.S. patents and has been elected an IEEE Fellow. In April 2010 he was recognized by the newspaper The Oregonian as the most prolific inventor in the State of Oregon. In 2013 Chau was elected a member of the U.S. National Academy of Engineering.